In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area, as typically the number of interconnections required increases in an over-proportional manner relative to the number of circuit elements. Thus, a plurality of stacked wiring layers, also referred to as metallization layers, are usually provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called conductive vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific integrated circuits) and the like.
With reduced space between individual metal lines within a metallization layer, it becomes difficult to form a conductive via in electrical connection with one metal line while maintaining sufficient insulation between the conductive via and the adjacent metal line. For example, an overlay error during via formation may result in too little insulation between the conductive via and the adjacent metal line. As a result, time dependent dielectric breakdown (TDDB) may occur in the dielectric material located between the conductive via and the adjacent metal line.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that provide improved self-aligned vias. Additionally, it is desirable to provide integrated circuits and methods for fabricating integrated circuits in which vias are self-aligned with a lower metal line in a first orientation or direction and are self-aligned with an upper metal line in second orientation or direction that is transverse or perpendicular to the first orientation. Also, it is desirable to provide methods for the fabrication of such structures that are easily integrated into existing process flow schemes used in semiconductor fabrication facilities. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.